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IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 28 features ? 168 pin jedec standard, 8 byte dual in-line memory module ? 4mx64 extended data out page mode dimm ? performance: ? all inputs and outputs are lvttl (3.3v) or ttl (5.0v) compatible ? single 3.3v 0.3v or 5v 0.5v power supply ? au contacts ? optimized for byte-write non-parity applications ? system performance bene?ts: - buffered inputs (except ras, data) - reduced noise (32 v ss /v cc pins) - 4 byte interleave enabled - byte write, byte read accesses - buffered pds ? edo mode, read-modify-write cycles ? refresh modes: ras-only, cbr and hidden refresh ? 2048 refresh cycles distributed across 32ms (11/11 addressing) ? 4096 refresh cycles distributed across 64ms (12/10 addressing) ? 12/10 or 11/11 addressing (row/column) ? card size: 5.25" x 1.0" x 0.354" ? drams in soj package description IBM11M4645B/c is an industry standard 168-pin 8-byte dual in-line memory module (dimm) which is organized as a 4mx64 high speed memory array designed with edo drams for non-parity applica- tions. the dimm uses 16 4mx4 edo drams in soj packages. the use of edo drams allows for a reduction in page mode cycle time from 40ns (fast page) to 25ns for 60ns dram modules. improved system performance is provided by the on-dimm buffering of selected input signals. the specified timings include all buffer, net and skew delays, which simplifies the memory subsystem design analysis. the data and ras signals are not buffered, which preserves the dram access specifi- cations of 60ns and 70ns. presence detect (pd) and identification detect (id) bits provide information about the dimm density, addressing, performance and features. pd bits can be dotted at the system level and activated for each dimm position using the pd enable ( pde) signal. id bits also allow detection of card features, and may be dot-ord at the system level to provide information for the entire dimm bank. for example, if a x64 par- ity dimm were inserted into a bank of x72 parity dimms, id0 (grounded) would indicate that at least one dimm in that memory bank is x64, and if the memory controller is designed to do so, all dimms in that memory bank will function as x64s. all ibm 168-pin dimms provide a high performance, flexible 8-byte interface in a 5.25 long space-saving footprint. related products are the x72 parity (5v) and ecc dimms (5v and 3.3v). -60 -70 t rac ras access time 60ns 70ns t cac cas access time 20ns 25ns t aa access time from address 35ns 40ns t rc cycle time 104ns 124ns t hpc edo mode cycle time 25ns 30ns card outline (3.3v) 1 85 10 94 11 95 40 124 41 125 84 168 (front) (back) see detail a detail a for 5.0v version ibm11m4730c4m x 72 e12/10, 5.0v, au. discontinued (9/98 - last order; 3/99 last ship)
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 28 50h4198 sa14-4618-05 revised 1/97 IBM11M4645B ibm11m4645c 4m x 64 dram module pin description ras0, ras2 row address strobe cas0 - cas7 column address strobe (buffered) we0, we2 read/write input (buffered) oe0, oe2 output enable (buffered) a0, b0, a1 - a11 address inputs (buffered) dqx data input/output v cc power (3.3v or 5.0v) v ss ground nc no connect pd1 - pd8 presence detects (buffered) pde presence detect enable id0 - id1 id bits pinout pin# front side pin# back side pin# front side pin# back side 1 v ss 85 v ss 43 v ss 127 v ss 2 dq0 86 dq36 44 oe2 128 nc 3 dq1 87 dq37 45 ras2 129 nc 4 dq2 88 dq38 46 cas4 130 cas5 5 dq3 89 dq39 47 cas6 131 cas7 6 v cc 90 v cc 48 we2 132 pde 7 dq4 91 dq40 49 v cc 133 v cc 8 dq5 92 dq41 50 nc 134 nc 9 dq6 93 dq42 51 nc 135 nc 10 dq7 94 dq43 52 dq18 136 dq54 11 dq8 95 dq44 53 dq19 137 dq55 12 v ss 96 v ss 54 v ss 138 v ss 13 dq9 97 dq45 55 dq20 139 dq56 14 dq10 98 dq46 56 dq21 140 dq57 15 dq11 99 dq47 57 dq22 141 dq58 16 dq12 100 dq48 58 dq23 142 dq59 17 dq13 101 dq49 59 v cc 143 v cc 18 v cc 102 v cc 60 dq24 144 dq60 19 dq14 103 dq50 61 nc 145 nc 20 dq15 104 dq51 62 nc 146 nc 21 dq16 105 dq52 63 nc 147 nc 22 dq17 106 dq53 64 nc 148 nc 23 v ss 107 v ss 65 dq25 149 dq61 24 nc 108 nc 66 dq26 150 dq62 25 nc 109 nc 67 dq27 151 dq63 26 v cc 110 v cc 68 v ss 152 v ss 27 we0 111 nc 69 dq28 153 dq64 28 cas0 112 cas1 70 dq29 154 dq65 29 cas2 113 cas3 71 dq30 155 dq66 30 ras0 114 nc 72 dq31 156 dq67 31 oe0 115 nc 73 v cc 157 v cc 32 v ss 116 v ss 74 dq32 158 dq68 33 a0 117 a1 75 dq33 159 dq69 34 a2 118 a3 76 dq34 160 dq70 35 a4 119 a5 77 dq35 161 dq71 36 a6 120 a7 78 v ss 162 v ss 37 a8 121 a9 79 pd1 163 pd2 38 a10 122 a11 80 pd3 164 pd4 39 nc 123 nc 81 pd5 165 pd6 40 v cc 124 v cc 82 pd7 166 pd8 41 nc 125 nc 83 id0 167 id1 42 nc 126 b0 84 v cc 168 v cc note: all pin assignments are consistent for all 8 byte versions. ordering information part number organization speed addr. leads dimension power IBM11M4645B-60j 4mx64 60ns 11/11 au 5.25x1.0x 0.354 5.0v ibm11m4645c-60j 60ns 12/10 ibm11m4645c-70j 70ns ibm11m4645cb-60j 60ns 3.3v ibm11m4645cb-70j 70ns discontinued (9/98 - last order; 3/99 last ship)
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 28 50h4198 sa14-4618-05 revised 1/97 IBM11M4645B ibm11m4645c 4m x 64 dram module block diagram dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq31 dq32 dq33 dq34 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d0 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 v cc v ss d0 - d15, buffers d0 - d15, buffers a1 - an a1-an: drams d0 - d15 a0 a0: drams d0-d7 b0 a0: drams d8-d15 we0 ras0 oe0 d1 d2 d3 d4 d5 d7 dq27 dq28 dq29 dq30 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d6 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq67 dq68 dq69 dq70 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d8 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 we2 ras2 oe2 d9 d10 d11 d12 d13 d15 dq63 dq64 dq65 dq66 cas ras we oe i/o 0 i/o 1 i/o 2 i/o 3 d14 v ss pd 1-8 (when = 0, 1=nc) cas1 cas2 cas0 cas7 cas4 cas5 cas6 cas3 pde discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 28 50h4198 sa14-4618-05 revised 1/97 truth table function ras cas we oe row address column address pde dqx standby h h ? x xxxxx high impedance read l l h l row col x valid data out early-write l l l x row col x valid data in late-write l l h ? l h row col x valid data in rmw l l h ? ll ? h row col x valid data out, valid data in edo page mode - read 1st cycle l h ? l h l row col x valid data out subsequent cycles l h ? l h l n/a col x valid data out edo page mode - write 1st cycle l h ? l l x row col x valid data in subsequent cycles l h ? l l x n/a col x valid data in edo page mode - rmw 1st cycle l h ? lh ? ll ? h row col x valid data out, valid data in subsequent cycles l h ? lh ? ll ? h n/a col x valid data out, valid data in ras-only refresh l h x x row n/a x high impedance cas-before- ras refresh h ? l lhxxxx high impedance hidden refresh read l ? h ? l l h l row col x data out write l ? h ? l l h x row col x data in read presence detects xxxxxxl not affected (pd bits valid) presence detect pin -60 -70 pd1 (pd1 - pd4: addressing/density) 1 1 pd2 11 pd3 00 pd4 11 pd5 (edo detection) 11 pd6 (pd6 - pd7: speed) 10 pd7 11 pd8 (parity/ecc designator) 1 1 id0 (dimm type/width) 00 id1 (refresh mode) 00 1. pd1-8 are buffered outputs (0 = driven to v ol , 1 = open) 2. id0-1 are unbuffered outputs (0 = v ss , 1 = open) 3. pde should be tied high or low at system level if not used discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 28 absolute maximum ratings symbol parameter rating (3.3v) rating (5.0v) units notes v cc power supply voltage -0.5 to +4.6 -1.0 to +7.0 v 1 v in input voltage -0.5 to min (v cc + 0.5, 4.6) -0.5 to min (v cc + 0.5, 7.0) v1 v out output voltage -0.5 to min (v cc + 0.5, 4.6) -0.5 to min (v cc + 0.5, 7.0) v1 t opr operating temperature 0 to +70 0 to +70 c 1 t stg storage temperature -55 to +125 -55 to +125 c 1 p d power dissipation 11/11 addr n/a 7.5 w 1, 2 12/10 addr. 4.3 6.6 i out short circuit output current 50 50 ma 1 i outpd short circuit output current (pd) 60 60 ma 1 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated is not implied. exposure to absolute maximum rating con- dition for extended periods may affect reliability. 2. maximum power occurs when all banks are active (refresh cycle). recommended dc operating conditions (t a = 0 to 70 c) symbol parameter 3.3v 5.0v units notes min typ max min typ max v cc supply voltage 3.0 3.3 3.6 4.5 5.0 5.5 v 1 v ih input high voltage 2.0 v cc + 0.5 2.4 v cc + 0.5 v 1, 2 v il input low voltage -0.5 0.8 -0.5 0.8 v 1, 2 1. all voltages referenced to v ss. 2. v ih may overshoot to v cc + 1.2v for pulse widths of 4.0ns with 3.3 volt, or v cc + 2.0v for pulse widths of 4.0ns (or v cc + 1.0v for 8.0ns) with 5.0 volt. additionally, v il may undershoot to -2.0v for pulse widths 4.0ns (or -1.0v for 8.0ns). pulse widths measured at 50% points with amplitude measured peak to dc reference. capacitance (t a = 0 to +70 c, v cc = 3.3v 0.3v or 5.0v 0.5v) symbol parameter max units c i1 input capacitance (a0, b0, a1-a11) 90 pf c i2 input capacitance ( ras) 70 pf c i3 input capacitance ( cas, we, oe) 13 pf c i4 input capacitance ( pde) 18 pf c io1 input/output capacitance (dq x )15pf c o1 output capacitance (pd) 15 pf c o2 output capacitance (id) 5pf discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 28 50h4198 sa14-4618-05 revised 1/97 dc electrical characteristics (t a = 0 to +70 c, v cc = 3.3v 0.3v) 12/10 addressing 11/11 addressing symbol parameter min max min max units notes i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min) -60 1200 1360 ma 1, 2, 3 -70 1040 1200 i cc2 standby current (ttl) power supply standby current ( ras = cas 3 v ih ) 32 32 ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas 3 v ih : t rc = t rc min) -60 1200 1360 ma 1, 3 -70 1040 1200 i cc4 fast page mode current average power supply current, fast page mode ( ras v il , cas, address cycling: t pc = t pc min) -60 1040 1040 ma 1, 2, 3 -70 880 880 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) 18 18 ma i cc6 cas before ras refresh current average power supply current, cas before ras mode ( ras, cas, cycling: t rc = t rc min) -60 1200 1360 ma 1, 3 -70 1040 1200 i i(l) input leakage current input leakage current, any input (0.0 v in (v cc < 6.0v)), all other pins not under test = 0v all but ras -10 +10 -10 +10 m a ras -18 +18 -18 +18 i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -2 +2 -2 +2 m a v oh output high level output h level voltage (i out = -2ma @ 2.4v) 2.4 2.4 v v ol output low level output l level voltage (i out = +2ma @ 0.4v) 0.4 0.4 v 1. i cc1 ,i cc3 ,i cc4 and i cc6 depend on cycle rate. 2. i cc1 ,i cc4 depend on output loading. speci?ed values are obtained with output open. 3. address can be changed once or less while ras = v il . in the case of i cc4 , it can be changed once or less when cas = v ih. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 28 ac characteristics (t a = 0 to +70 c, v cc = 3.3v 0.3v or 5.0v 0.5v) 1. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 2. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required. 3. the speci?ed timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the dram device timings. the data and ras signals are not buffered, which preserves the drams access speci?cations of 60ns and 70ns. 4. ac measurements assume t t = 2ns. . read, write, read-modify-write and refresh cycles (common parameters) symbol parameter -60 -70 unit notes min max min max t rc random read or write cycle time 104 124 ns t rp ras precharge time 40 50 ns t cp cas precharge time 10 10 ns t ras ras pulse width 60 10k 70 10k ns t cas cas pulse width 10 10k 12 10k ns t asr row address setup time 5 5 ns t rah row address hold time 8 8 ns t asc column address setup time 2 2 ns t cah column address hold time 10 10 ns t rcd ras to cas delay time 12 40 12 45 ns 1 t rad ras to column address delay time 10 25 10 30 ns 2 t rsh ras hold time 15 17 ns t csh cas hold time 48 53 ns t crp cas to ras precharge time 10 10 ns t odd oe to d in delay time 2025ns 3 t dzo oe delay time from d in -2 -2 ns 4 t dzc cas delay time from d in -2 -2 ns 4 t t transition time (rise and fall) 2 30 2 30 ns 1. operation within the t rcd (max) limit ensures that t rac (max) can be met. the t rcd (max) is specified as a reference point only: if t rcd is greater than the specified t rcd (max) limit, then access time is controlled by t cac. 2. operation within the t rad (max) limit ensures that t rac (max) can be met. the t rad (max) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa. 3. either t cdd or t odd must be satis?ed. 4. either t dzc or t dzo must be satis?ed. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 28 50h4198 sa14-4618-05 revised 1/97 write cycle symbol parameter -60 -70 unit notes min max min max t wcs write command set up time 2 2 ns 1 t wch write command hold time 12 14 ns t wp write command pulse width 10 12 ns t rwl write command to ras lead time 15 17 ns t cwl write command to cas lead time 12 14 ns t ds d in setup time -2 -2 ns 2 t dh d in hold time 15 17 ns 2 1. t wcs , t rwd , t cwd , and t awd are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.)and t awd 3 t awd (min.), the cycle is a read-modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. 2. data-in set-up and hold is measured from the latter of the two timings, cas or we. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 28 read cycle symbol parameter -60 -70 unit notes min max min max t rac access time from ras 60 70 ns 1, 2 t cac access time from cas 20 25 ns 1, 2 t aa access time from address 35 40 ns 1, 2 t oea access time from oe 2025ns 1, 2 t rcs read command setup time 2 2 ns t rch read command hold time to cas 2 2 ns 3 t rrh read command hold time to ras 0 0 ns 3 t ral column address to ras lead time 35 40 ns t clz cas to output in low-z 2 2 ns t oes oe setup time prior to cas 10 10 ns t ord oe setup time prior to ras (hidden refresh) 5 5 ns t cdd cas to d in delay time 2020ns 5 t oez output buffer turn-off delay from oe 2 20 2 20 ns 4 t off output buffer turn-off delay 2 20 2 20 ns 4, 6 1. measured with the speci?ed current load and 100pf. 2. access time is determined by the latter of t rac , t cac , t cpa , t aa, t oea . 3. either t rch or t rrh must be satis?ed. 4. t off (max) and t oez (max) de?ne the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 5. either t cdd or t odd must be satis?ed. 6. t off is referenced from the rising edge of ras or cas , whichever is last. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 28 50h4198 sa14-4618-05 revised 1/97 read-modify-write cycle symbol parameter -60 -70 unit notes min max min max t rwc read-modify-write cycle time 143 170 ns t rwd ras to we delay time 82 97 ns 1 t cwd cas to we delay time 44 54 ns 1 t awd column address to we delay time 57 67 ns 1 t oeh oe command hold time 10 12 ns 1. t wcs , t rwd , t cwd , and t awd are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.)and t awd 3 t awd (min.), the cycle is a read-modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. edo mode cycle symbol parameter -60 -70 units notes min. max. min. max. t hcas cas pulse width (edo page mode) 10 10k 12 10k ns t hpc edo page mode cycle time (read/write) 25 30 ns t hprwc edo page mode read modify write cycle time 72 84 ns t doh data-out hold time from cas 10 10 ns t whz output buffer turn-off delay from we 2 15 2 20 ns t wpz we pulse width to output disable at cas high 10 10 ns t cprh ras hold time from cas precharge 40 45 ns t cpa access time from cas precharge 40 45 ns 1 t rasp edo page mode ras pulse width 60 125k 70 125k ns t oep oe high pulse width 10 10 ns t oehc oe high hold time from cas high 10 10 ns 1. measured with the specified current load and 100pf at v ol = 0.8v and v oh = 2.0v. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 28 refresh cycle symbol parameter -60 -70 unit notes min max min max t chr cas hold time ( cas before ras refresh cycle) 88ns t csr cas setup time ( cas before ras refresh cycle) 1010ns t wrp we setup time ( cas before ras refresh cycle) 1515ns t wrh we hold time ( cas before ras refresh cycle) 88ns t rpc ras precharge to cas hold time 3 3 ns t ref refresh period 3232ms 1 6464ms 2 1. 11/11 addressing: 2048 refreshes are required every 32ms. 2. 12/10 addressing: 4096 refreshes are required every 64ms. presence detect read cycle symbol parameter -60 -70 unit notes min max min max t pd pde to valid presence detect data 10 10 ns 1 t pdoff pde inactive to presence detects inactive 0 10 0 10 ns 2 1. measured with the specified current load and 100pf. 2. t pdoff (max) de?nes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 28 50h4198 sa14-4618-05 revised 1/97 read cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rcs t dzc t clz t cac t rac hi-z hi-z t rrh : h: or l t rcd t oez hi-z t rsh t ral t dzo t aa t oea cas t odd t cdd t rch t off t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 28 write cycle (early write) t rc ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rcd t csh t crp t rah t asc t cah t asr t rad t wcs hi-z : h or l valid data in t wch t ds t dh t cas t rsh t wp cas t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 28 50h4198 sa14-4618-05 revised 1/97 write cycle (late write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rwl : h or l t wp t cwl valid data in hi-z hi-z t dzo t oez t clz t ds t rcd t dh t rcs * * t oeh greater than or equal to t cwl hi-z t rsh t dzc t oea t oeh t odd cas t wrp note 1 t wrp t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 28 read-modify-write-cycle d in t oeh v ol v oh v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih t rcd t rwc t ras t csh t cas t rp t rah t asc t asr t cah t cwd t rcs t oea t rwl t cwl t wp t dh t ds t dzc t cac t clz t odd t oez t rac ras address we oe d in d out hi-z hi-z d out row column : h or l * t oeh greater than or equal to t cwl * hi-z t crp t awd t aa t rwd t rsh t rad t dzo cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 28 50h4198 sa14-4618-05 revised 1/97 edo page mode read cycle t rp t hcas data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t doh t doh t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t wp t cac data out n t off cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 28 edo page mode read cycle ( oe control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off t oea t oez t oez t oea cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes t hcas t oes t oehc t oep t oehc t oep t oes discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 28 50h4198 sa14-4618-05 revised 1/97 edo page mode read cycle ( we control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes t hcas t wpz t wpz t rch t rcs t rcs t rch t whz t whz discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 28 edo page mode early write cycle t hcas t rp ras row address we column 1 column 2 column n data in 1 data in 2 data in n t asr t rah t cah t wch t dh d in t rasp t rsh t hcas t hcas t hpc t rad t asc t asc t csh t cah t asc t cah t wch t wcs t wch t wcs t wcs t ds t ds t dh t dh t ds : h or l t cwl t rwl t wp t wp t wp oe = dont care v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t ral discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 28 50h4198 sa14-4618-05 revised 1/97 edo page mode late write cycle t hcas t rp ras row address we column 1 column 2 column n oe data in 1 data in 2 data in n t asr t rah t asc t asc t asc t cah t cah t cah t cwl t wp t cwl t wp t cwl t wp t oeh t oeh t oeh t ds t dh t odd t ds t dh t odd t ds t dh d in : h or l t rasp t rsh t hcas t hcas t hpc t csh t odd hi-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp t rad t rcs t rcs t rcs t rwl cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 28 edo page mode read modify write cycle address ras we oe d out d in d in d in t rp t cp t cp t asr t rad t rah t cah t asc t asc t cah t asc t cah t wp t cwl t wp t rcs t rcs t wp t cwl t rwl t cac t oeh t oeh t oeh d out d out t clz t clz t odd t odd t dh t dh t clz t odd t dh d in d out : h or l hi-z hi-z t rasp t cas t hprwc t cas t ral t awd t cwd t aa t cpa t aa t awd t cwd t rwd t awd t cwd t rcs t rac t aa t oea t oea t cac t cac t oea t oez t oez t ds t ds t ds column 1 row column 2 column n t csh t oez v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rcd t cas t crp t cpa cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 28 50h4198 sa14-4618-05 revised 1/97 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z : h or l note: we, oe, d in are h or l t rpc t crp cas discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 28 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v oh v ol t ras t rp oe v ih v il d out v oh v ol hi-z : h or l t off t oez hi-z t odd t chr rc t t wrh t wrp t note: address is h or l rpc t cp t cdd t rpc t csr t wrh t wrp t csr cas discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 28 50h4198 sa14-4618-05 revised 1/97 hidden refresh cycle (read) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t ras t rp t rc t crp t rah t asc t cah t asr t rad t rcs t dzc t odd t oez t cdd t clz t cac t rac hi-z hi-z : h or l t rp t chr rsh t rcd t t rrh t wrp t wrh t rc t dzo t ral t off cas t oea t ord t aa hi-z discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 28 hidden refresh cycle (write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data t ras t ras t rp t rc t crp t rah t asc t cah t asr hi-z : h or l t rp t chr rsh t t ds t dh t wch wcs t t wrp t wrh t rc t wp t rcd cas discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 26 of 28 50h4198 sa14-4618-05 revised 1/97 presence detect read cycle pde v ih v il pd1-pd8 v oh v ol valid presence detect t pdoff * *pd pins must be pulled high at next level of assembly t pd discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module 50h4198 sa14-4618-05 revised 1/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 27 of 28 layout drawing 133.35 5.25 131.35 5.171 127.35 5.014 (2) 0 3.1877 .1255 65.68 2.586 6.35 .250 42.18 1.661 1.27 pitch .050 1.00 width .039 .157 (2x) 4.00 17.78 25.4 front 3.0 note: all dimensions are typical unless otherwise stated. 1.00 .700 .118 9.00 .354 max. side 5.232 1.27 0.10 .050 .004 + _ + _ .206 min. see detail a r 1.00 .0393 2.0 .078 3.0 .118 detail a scale 4/1 millimeters inches 5.232 .206 min. discontinued (9/98 - last order; 3/99 last ship)
IBM11M4645B ibm11m4645c 4m x 64 dram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 28 of 28 50h4198 sa14-4618-05 revised 1/97 revision log rev contents of modi?cation 08/95 initial release. 1/96 added 3.3v product reduced currents/power improved timings ( t cah, t chr, t csr ) 5/96 updated ordering information increased timings: t oes, t ord improved timings: t cah, t cdd, t oez, t off the cbr timing diagram was changed to allow cas to remain low for back-to-back cbr cycles. hidden refresh cycle (read) timing diagram was changed to show data being turned off with ras not cas 8/96 fixed typos 12/96 updated ordering information new card size (1 tall) 1/97 added 11/11 addressing for 5v offering discontinued (9/98 - last order; 3/99 last ship)
intern ational business machines corp.1997 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. formid ? discontinued (9/98 - last order; 3/99 last ship)

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